FIG. 6A is a diagram illustrating a configuration example of a parallel-type analog-digital converter (AD converter). FIG. 6A illustrates a parallel-type AD converter (flash AD converter) that converts input analog input signals to n-bit (n being a natural number) digital signals DO[n-1:0]. In FIG. 6A, R0 to Rm (m=2n−1) represent resistors, CMP1 to CMPm represent comparators (comparators), and ENC represents an encoder.
The resistors R0 to Rm are connected in series between a power supply terminal to which a reference voltage VB on the low potential side is supplied and a power supply terminal to which a reference voltage VT on the high potential side is supplied in the order of the resistors R0, R1, R2, . . . , R(m−3), R(m−2), R(m−1), and Rm. With i being an integer of 1 to m, a potential at a connection point REF<i> between the resistor R(i−1) and the resistor Ri is input to the comparators CMP1 to CMPm as a comparison reference potential VREF<i>. That is, a resistor ladder circuit configured by the resistors R0 to Rm resistance-divides the voltage between the voltage VB and the voltage VT to thereby generate the comparison reference potentials VREF<i> and supplies them to the comparators CMP1 to CMPm.
To the comparator CMPi, an analog input signal VINP input through an input terminal INP and an analog input signal VINN input through an input terminal INN are input. Further, to the comparator CMPi, the comparison reference potential VREF<i> being the potential at the connection point REF<i> in the resistor ladder circuit and a comparison reference potential VREF<m−i+1> being a potential at a connection point REF<m−i+1> in the resistor ladder circuit are input. The comparator CMPi compares a difference (a difference voltage) between the comparison reference potential VREF<i> and the analog input signal VINP and a difference (a difference voltage) between the comparison reference potential VREF<m−i+1> and the analog input signal VINN to output a result of the comparison. The encoder ENC receives results of the comparisons of the respective comparators CMPi to encode them and converts the resultants to the digital signals DO[n-1:0] to output them.
In the previously described parallel-type AD converter, the comparators are made to operate in parallel and perform the comparisons of the analog input signals and the plural comparison reference potentials in parallel, and thereby AD conversion can be performed at high speed. On the other hand, in the case of an n-bit parallel-type AD converter (total-bit flash AD converter), for example, (2n−1) pieces of comparators are required and power consumption increases. However, in recent years, achievement of low power of the comparators advances, and power consumption in the resistor ladder circuit accounts for a large percentage of power consumption of the parallel-type AD converter.
Here, in the parallel-type AD converter illustrated in FIG. 6A, the resistor ladder circuit that supplies the comparison reference potentials VREF<i> to the comparators CMP1 to CMPm and is configured by the resistors R0 to Rm is an important element circuit, and the accuracy of the resistor ladder circuit affects the accuracy of the whole parallel-type AD converter. Noises from the comparators CMP1 to CMPm are one of the causes of accuracy deterioration of the resistor ladder circuit. By noise currents In to generate in the process of operation of the comparators CMP1 to CMPm, the potentials VREF<i> at the connection points REF<i> in the resistor ladder circuit vary, and with respect to an ideal comparison reference potential indicated by LV61 in FIG. 6B, for example, the comparison reference potential varies as indicated by LV62. The variation in the comparison reference potential VREF<i> caused by the noise currents In increases a conversion error in the AD conversion and thereby the accuracy of the parallel-type AD converter deteriorates. Conventionally, a bias current Ibias in the resistor ladder circuit has been set to be sufficiently larger than the noise current In and an effect caused by the noise currents In has been decreased extremely, and thereby the accuracy deterioration of the parallel-type AD converter has been suppressed.
There has been proposed a technique of suppressing an effect of kickback noise to generate because of switching operations while suppressing an increase in circuit formation area in an AD converter provided with a switched capacitor integration circuit (see Patent Literature 1).
However, when the bias current Ibias in the resistor ladder circuit is set to be sufficiently larger than the noise current In in order to suppress the accuracy deterioration of the parallel-type AD converter as described previously, there is caused a problem that the power consumption in the resistor ladder circuit increases.